| 摘要 |
PURPOSE:To contrive to simplify the constitution of a parallel data circuit by inputting one of two kinds of data sequence before conversion selectively to a data converting means and composing parallel data of the specific number of bits. CONSTITUTION:This circuit generates and outputs parallel data in three kinds of formats selectively. When parallel data in the 1st format is outputted, a binary-coded signal 21 is supplied to the serial signal input terminal of an 8-bit shift register 51. While mode setting data 54 specifies a 1st format, the data is inputted, bit by bit, and shifted in synchronizing with a clock signal 52. Then while data corresponding to eight bits, i.e. eight picture elements is set, the data is outputted as parallel data 38. The 2nd selector 58 selects output data 61 obtained by dividing the frequency of the clock signal 56 by eight. This is used as a write clock 42 to write the parallel data 38 in a line buffer 39. Thus, parallel data of every eight picture elements is sent out as an output 44. |
