| 摘要 |
In a frequency synthesizer, a variable frequency divider divides the oscillation signal of a VCO while switching the frequency dividing ratio in accordance with an integral frequency dividing ratio generated by a frequency dividing ratio generating circuit. The VCO is controlled with an output of a loop filter. The frequency dividing ratio generating circuit includes multiple integrators connected in cascade and differentiators which differentiate the carry-out signals of the integrators, so that a phase error generated at the variable frequency divider is obtained from an output of an adder included in the final stage integrator of the frequency dividing ratio generating circuit. A phase error compensation value is output, and further a pulse width of a signal to be used for compensating for phase error is varied in accordance with the phase error compensation value to perform compensation for the phase error.
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