发明名称 CALCULATION SYSTEM FOR PROPAGATION DELAY TIME
摘要 PURPOSE:To easily calculate a propagation delay time by inverting the output of a 1st stage FF circuit of a scan path and inputting the inverted output to the 1st stage FF circuit, and observing the output waveform when a clock signal supplied to FF circuits is made gradually fast. CONSTITUTION:A FF circuit 2-i (i=1-n) operates in synchronization with the clock signal 7 received through a clock terminal normally to input a data input 9-i and sends its output out. A test mode signal 5 is inputted to a selector circuit 1 and a shift mode signal 6 is supplied to a shift mode terminal; and then respective FF circuits 2-i are connected in series to form scan paths and the output data of the selector circuit 1 is passed. In this state, the output of the FF circuit 2-1 is inverted by a NAND circuit 3 and applied to the selector circuit 1 to make the clock signal 7 fast gradually. The output 8 at this time is observed to calculate the propagation delay time of the whole IC.
申请公布号 JPS6367578(A) 申请公布日期 1988.03.26
申请号 JP19860213402 申请日期 1986.09.10
申请人 NEC CORP 发明人 INOUE KAZUHISA
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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