发明名称 |
MICROPROCESSOR CONTAINING ANALOG/DIGITAL CONVERSION MECHANISM |
摘要 |
<p>PURPOSE:To reduce a hardware load by using a capture circuit which fetches a counted data from a time base counter when the edge of an output signal of a comparator arrives and sends the fetching result to an arithmetic means or a memory means with a specific instruction given from an instruction executing means. CONSTITUTION:Both a capture controller 800 and a capture register block 700 fetch the counted data having the minimum decomposition accuracy higher than the instruction executing cycle from a time base counter 500 when the edge of a capture signal arrives. This fetching result is sent to a computing element ALU300, or a register 100 or a RAM200 via a capture circuit with a specific instruction given from an instruction executing circuit 400. In such a manner, since a mechanism serving as a capture circuit is used to a scan counter for conversion and a register which stores the conversion results, the hardware load is considerably reduced.</p> |
申请公布号 |
JPS6367667(A) |
申请公布日期 |
1988.03.26 |
申请号 |
JP19860212232 |
申请日期 |
1986.09.09 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
MIZUGUCHI HIROSHI;OOTA YUTAKA;SAKAI TOSHIHIKO |
分类号 |
H03M1/12;G06F3/05;G06F15/78 |
主分类号 |
H03M1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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