| 摘要 |
PURPOSE:To suppress an area loss due to a mask aligning margin in a cell to the minimum limit, to effectively prevent an electric interference between cells and to be able to achieve 1-2 mum<2> of cell area by forming a capacitor on the lower part of the side of an insular silicon divided by latticelike grooves, and forming MIS FET on the top of the side. CONSTITUTION:A second conductivity type first semiconductor layer 2 and a first conductivity type second semiconductor layer 3 are laminated on a first conductivity type semiconductor substrate 1, and the layers 2, 3 are insularly separated by latticelike grooves of the depth which arrives at a substrate 1. First insulating films 9 are formed on the side of the layer 2 and in the bottom of the groove, a first conductor 10 is buried in the bottom of the groove through the film 9 on the side of the layer 2, and a capacitor 41 is formed by the layer 2, the film 9 and the conductor 10. A second conductivity type diffused layer 16 is formed on the upper surface of the layer 3, a second insulating film 12 is formed on the side of the layer 3, a second conductor 13 is formed in the groove on the film 12 by insulating it from the conductor 10, and an FET 42 is formed of the layers 2, 3, the layer 16, the film 12 and the conductor 13. |
