发明名称
摘要 <p>PURPOSE:To ensure the eacy contermeasure to the increment of the circuit number by forming the switching device as the repeater including the circuit switching circuit. CONSTITUTION:The following circuits are installed to receiver 21-1: equalization circuit 31-1 incorporating the peak value detection and AGC functions; timing extraction circuit 32-1 which extracts the clock component out of the digital data; and identification/regeneration circuit 33-1 which gives the identification and regeneration to the digital data in the extracted timing. These circuits are also rovided to receiver 21-2 as well. On the other hand, timing extraction circuit 34-1 and U/S converter 35-1 which converts the uni-polar signal into the transmission signal are installed to transmitter 22-1.</p>
申请公布号 JPS6313383(B2) 申请公布日期 1988.03.25
申请号 JP19790016004 申请日期 1979.02.16
申请人 FUJITSU LTD 发明人 SHIMOI KOICHI;NISHIZAKI KOJI
分类号 H04B3/00;H04L7/027;H04L25/03;H04L25/24;H04L25/52 主分类号 H04B3/00
代理机构 代理人
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