| 摘要 |
<p>In a matrix array of nonvolatile memory cells, each cell (36) includes a floating gate (47) coupled by large and small capacitances (46, 44) to first and second substrate regions (42, 43). The cell (36) further includes first and second select transistors (49, 51) having gate electrodes enabled by a row line and source/drain paths coupled respectively between the first and second substrate regions (42, 43), and first and second column lines (IOC1, R1). The first and second substrate regions (42, 43) communicate with corresponding second and first substrate regions of adjacent cells in the row. Programming and reading of the cell involves applying appropriate voltages to the first and second column lines (IOC1, R1) and the first column line (I1C2) of an adjacent cell. Such sharing of column lines between adjacent cells enables a high packing density to be achieved.</p> |
