| 摘要 |
PURPOSE:To enable the width of a gate to be enlarged and to enable unit cells to be supplied with power without obstructing interconnection within the unit cells, by providing feed regions for feeding power to a well and a substrate near the center of the unit cells and connecting the feed regions to supply wiring or ground wiring by means of silicide layers. CONSTITUTION:Aluminium wiring layers 16, 17 connected to a power supply and ground are provided at the upper and lower ends of unit cells 1, 2 while feeding regions 7, 10 for feeding power to a well and a semiconductor substrate are provided near the center of the unit cells, and the wiring layers 16, 17 are connected to the feeding regions 7, 10 by means of low resistance layers 8 provided in the drain/source of an FET. Since the well and the feeding regions 7, 10 of the semiconductor substrate are provided near the center of the unit cells 1, 2, the width of the gate of the FET can be enlarged without obstruction thereof. Further, since the aluminium layers 16 providing the supply wirings are provided at the upper and lower ends of the unit cells 1, 2 and they are connected to the feed regions by means of the low resistance layers 8 provided in the drain/source, interconnection within the unit cells can be realized by these aluminium layers without obstruction. |
