APPARATUS FOR GENERATING DATA RECOGNITION SIGNAL FOR VME BUS

摘要

PURPOSE: An apparatus for generating a data recognition signal for a VME bus is provided to correct a timing system between a VME bus interface board and a universal SPARC CPU control board by generating a data recognition signal for a VME bus. CONSTITUTION: An apparatus for generating a data recognition signal for a VME bus comprises generating part(110) for signal of selecting a board, a first buffer(120), a first latch(130), a second buffer(140), a second latch(150), and a generating part(160) for signal of recognizing a data. The generating part(110) for signal of selecting a board generates a board selection signal. The first buffer performs buffering for the board selection signal. The first latch latches the buffered signal. The second buffer performs the buffering for the latched signal. The second latch latches the buffered signal. The generating part(160) for signal of recognizing a data outputs a data recognition signal.