HIGH-SPEED VITERBI DECODER

摘要

PURPOSE: A high-speed viterbi decoder is provided to increase the operation speed of a viterbi decoder by calculating a new stage matrix value per N clocks, or by calculating a new stage matrix value at two stages by one calculation per two clocks. CONSTITUTION: In a high-speed viterbi decoder, a 1/N divider(207) generates an auxiliaryy clock having a 1/N frequency of a main clock, and a branch matrix calculator(201) calculates respective branch matrix values at a predetermined transfer function which is modeled by the usage of input data by a period of the main clock. A serial/parallel data converter(202) outputs the calculated branch matrix values in parallel by an N-stage unit in the period of the main clock. An add/comparison selector(203) calculates an euclidean distance of a stage matrix value of a previous N stage being transient to a stage by the usage of the matrix values of the serial/parallel data converter in the period of the auxiliary clock. The selector(203) compares the calculated results, and determines the result of the minimum value as a new stage matrix value.