发明名称 PROCESSING SYSTEM FOR PARITY ERROR
摘要 PURPOSE:To evade that a normal device is judged to be abnormal and an error processing is executed by providing means, etc., to check whether or not a parity error is obtained when an abnormality exists at parity checking and interruption is executed. CONSTITUTION:When data in a memory are read, the data and a parity bit to the data are collated, parity checking is always executed and when the abnormality exists, NMI (Non-Maskable Interrupt) is raised. Thus, it is checked whether or not a parity error is obtained, and at the time of the parity error, an error retrying flag is turned on and re-reading is executed. In accordance with the memory area of the address of the memory, the data are read and parity checking is executed. As the result, when the parity error does not exist, the memory is normal, and therefore, a parity error retrying flag is turned off, and RTI (Return from Interrupt) is obtained. Thus, it can be evaded that a normal device is judged to be abnormal and the error processing is executed.
申请公布号 JPS6364147(A) 申请公布日期 1988.03.22
申请号 JP19860208338 申请日期 1986.09.04
申请人 FUJITSU LTD 发明人 YAMADA HIROKO;AZUMA MASAYUKI;YANO HIDEAKI
分类号 G06F12/16 主分类号 G06F12/16
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