| 摘要 |
PURPOSE:To speed up the operation of a dRAM and to reduce its power consumption by introducing a bit line sense amplifier which uses a bipolar transistor (TR) and a division bit line system. CONSTITUTION:Plural couples of division bit line DBL01 and -DBL01, DBL02 and -DBL02... are connected to main bit lines BL and -BL through MOS TRs Q1, Q2, Q5, Q7... as transfer gates, and the main bit lines BL and -BL are provided with differential amplifier type main bit line sense amplifiers MSAs (MSA0...MSAN) constituted by using bipolar TRs. Consequently, when data are read out of memory cells M1, M2..., a signal with a small logical amplitude from a bit line is detected by a differential amplifier using a bipolar TR, so high-speed operation is performed. Further, the power consumption for bit line discharging is a half as large as that of all bit lines and stored charges are discharged. |
