发明名称 PACKET SWITCHING SYSTEM
摘要 <p>PURPOSE:To constitute a large capacity of switch economically by combining the small capacity switch and a multiplexer circuit so as to constitute a packet switch thereby making each multiplexer circuit into an LSI. CONSTITUTION:An inputted packet is inputted in parallel with M-set of switches 208 via an input processing circuit 201. Each switch 205 reads an outgoing line number from a header of the packet and only the switch 208 accommodating the outgoing line fetches the data. The fetched data is written in the buffer memory and outputted to and output circuit designated by the header in time division. The packet outputted from the switch 203 is sent to a multiplexer circuit 204 provided in the unit of the outgoing line. The circuit 204 writes the data sent to each switch 205 into the buffer memory, adds a footer or the like by the output circuit to form a packet and sends the result to the outgoing line.</p>
申请公布号 JPS6362432(A) 申请公布日期 1988.03.18
申请号 JP19860206967 申请日期 1986.09.03
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SAKAKIBARA SO;TAKAHASHI TATSURO;KIKUCHI SHIRO;KATAOKA HIDEKI;YAMANAKA NAOAKI
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