发明名称 Analog/digital converter
摘要 The analog/digital converter exhibits a flip flop (1) and an input circuit switching over the output of the flip flop (1) at a fixed input switching threshold. A feedback network (8) connects the output of the flip flop (1) to the input of the input circuit (5). The input of the latter is connected to a mean-value-forming circuit. The input (7) for the analog voltage is connected to the input of the input circuit (5) by means of an input network (6). The output signal of the flip flop (1) is logically combined with a clock signal (TE) by at least one logic component (11). <IMAGE>
申请公布号 DE3630633(A1) 申请公布日期 1988.03.17
申请号 DE19863630633 申请日期 1986.09.09
申请人 BECKER,HENNING,DIPL.-ING. 发明人 BECKER,HENNING,DIPL.-ING.
分类号 H03M1/00 主分类号 H03M1/00
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