发明名称 COMPLEMENTARY 3-STATE MOS INTEGRATED CIRCUIT
摘要 PURPOSE:To contrive to reduce power consumption and a through-current of an output circuit at switching by inserting a resistor being an ON-resistance of a MOS transistor (TR) between gates of an output P-channel and N-channel MOS TR. CONSTITUTION:With a control input phi5 at L level and a control input, inverse of phi6 at H level, TRs P3, N3 are turned of, TRs P4, N4 are turned on and with an input terminal 1 at L level, TRs P2, P5, N1 are turned on, a TR P1 is turned off and an L level appears at an output terminal 2. With the input phi5 at H and the input, inverse of phi6 at L, the TRs P3, N3 are turned on and the TRs P4, N4 are turned off, the TRs P1, N1 are turned off regardless of the potential at the terminal 1 and the terminal 2 reaches a high impedance. A difference is supplied to the gate potential of the output circuit 12 at switching by connecting the 2nd analog switch SW7 used as a resistor and the 1st analog switch SW8 forming a 3-state in series between the gates of the TRs P1, N1 to decrease the through-current at switching, to reduce the spike voltage at switching and power consumption.
申请公布号 JPS6360625(A) 申请公布日期 1988.03.16
申请号 JP19860204262 申请日期 1986.08.29
申请人 MITSUBISHI ELECTRIC CORP 发明人 OKIDAKA TAKENORI;MIYAZAKI YUKIO
分类号 H03K19/0175;H03K17/60;H03K19/00;H03K19/0948 主分类号 H03K19/0175
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