| 摘要 |
PURPOSE:To reduce the area of a memory cell by electrically connecting a substrate region in an FET to a semiconductor substrate and positioning one part of one conduction electrode for the FET connected to a bit line onto a trench CONSTITUTION:A conductor layer 13 is arranged on the inner side wall of a trench through an insulating film 19 and constitute a charge storage region. and makes a round along the outer circumference of a cell, and a conductor layer 14 is disposed to the charge storage region through the insulating film 19 and organize a cell plate, and supplied with fixed potential. A P-type region 22 constructs a substrate region in an FET, and is connected electrically to a P-type substrate 11 through a P-type region 12. An N-type region 23 constitutes a first conduction electrode for the FET, and a bit line organized of a conductor layer 27 is connected to the N-type region 23. Accordingly, cells do not interfere mutually, large cell capacitance is acquired by shallow trench depth, a soft error rate is reduced, an element isolation region is made unnecessary, and the area of the cell can be minimized. |
