| 摘要 |
<p>A dynamic random access memory, including a memory (11), constituted by a plurality of dynamic type memory cells, a refresh control circuit (4) for refreshing the memory cells by controlling a refresh address circuit in a refresh mode, and an address latch circuit (6, 7) for latching an external address signal in a read/write mode and latching a refresh address signal in the refresh mode, also includes a clock generating circuit (1, 2) for generating a second clock (oB) and a third clock (oC) based on a first clock ( oA ) obtained after a predetermined delay time from a trailing edge of a row address strobe signal ( @RAS), the second clock (oB) controlling a first timing for taking the external address signal into the address latch circuit in the read/write mode, and the third clock being generated after the second clock and controlling a second timing for taking the refresh address signal into the address latch circuit in the refresh mode, thereby enabling higher operational speed of the DRAM to be achieved as compared with conventional DRAMs.</p> |
