发明名称 MULTIPLIER WITH ARITHMETIC LOGICAL OPERATION FUNCTION AND ITS DRIVING METHOD
摘要 PURPOSE:To contrive to attain high function by using an arithmetic logical operation circuit in the last addition stage of a partial product and adding a selector, which selects an input signal, to the input part of this arithmetic logical operation circuit. CONSTITUTION:A first operation mode is executed as follows; a first selector 4 is caused to select partial product signals 21...24 by a control signal C and partial products between first input signals X4-X1 and a second input signal Y4 are generated and outputted to a second selector 5 an an arithmetic logical operation circuit 3 is set to the addition mode to output the product between a first and second input signals as output signals Z8...Z1. In a second operation mode, namely, the arithmetic logical operation mode, the first selector 4 is caused to select second input signals Y4...Y1 by the control signal.C and the arithmetic logical operation circuit is set to the execution mode of AND, OR, exclusive OR, or other logical operations, addition, or subtraction between two input signals.
申请公布号 JPS6359627(A) 申请公布日期 1988.03.15
申请号 JP19860204899 申请日期 1986.08.29
申请人 NEC CORP 发明人 YAMASHINA MASAKATSU
分类号 G06F7/52;G06F7/00;G06F7/523;G06F7/53 主分类号 G06F7/52
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