| 摘要 |
PURPOSE:To obtain a phase control circuit with fact converging speed and equal stability by using an output of a phase comparator while not using a filter output for the next phase correction if a phase deviation is large and using the filter output when the phase synchronization is taken. CONSTITUTION:If the phase is deviated largely and the output of the filter 4 is positive through the result of phase comparison at a point A, the input to a decoder 12 is '1X' (X is'1' or '0'), resulting that a supervisory circuit 6 selects the output of the filter 4 as the output of a selection circuit 7. Thus, the frequency division ratio of a frequency division counter 5 is increased. When the phase is nearly matched and if the output of the filter 4 is positive through the phase comparison result at a point C, the input to the decoder 12 is 'IXO$, resulting that the supervisory circuit 6 selects the output of the filter 4 as the output of the selection circuit 7. Thus, the frequency division ratio of the frequency division counter 5 is unchanged. Thus, if the phase is synchronized, the effect of filter 4 is given. |
