发明名称 CONTROLLER FOR INTERRUPTION LEVEL OF I/O INTERFACE
摘要 PURPOSE:To easily change a set interruption level and to perform a setting test by providing a level setting device to an interface together with an interruption register, a pseudo interruption request generator and a comparator. CONSTITUTION:An interruption level of priority '1', for example, is first set to a levelsetting device 22 of an interface 2. A CPU 1 sets an interruption level of priority '3' to an interruption register 23 and delivers an interruption request signal of said level through a pseudo interruption request signal generator 25. A comparator 24 delivers no coincidence signal no coincidence is obtained between the level of said interruption request and the interruption level of the device 22. Thus the CPU 1 sets an interruption level of priority '2' to the register 23. In such as way, the CPU 1 sets successively the interruption levels 3, 2 and 1 to the register 23. While the comparator 24 performs successively comparisons and delivers a coincidence signal to the CPU 1 when the coincidence of comparison is obtained. The CPU 1 carries out an interruption routine based on the coincidence signal and in response to the interruption level of priority '1'.
申请公布号 JPS6358563(A) 申请公布日期 1988.03.14
申请号 JP19860201748 申请日期 1986.08.29
申请人 ANRITSU CORP 发明人 MATSUI MASAYUKI
分类号 G06F13/24 主分类号 G06F13/24
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