发明名称 PULSE GENERATING CIRCUIT
摘要 PURPOSE:To output a pulse with an always constant width independently of the width of a trigger input signal by controlling other RS flip-flop circuit so as not to be triggered again until the output of a pulse is finished after the circuit is triggered once by one RS flip-flop circuit. CONSTITUTION:When an input signal (a) is inputted, the 1st RS flip-flop circuit 11 is set and its Q output (g) changes from L to H. The change sets the 2nd RS flip-flop circuit 12 after a prescribed time. The Q output of the RS flip-flop circuit 12 resets the RS flip-flop circuit 12 resets the RS flip-flop circuit 11 through an inverter 16. Thus, a pulse having a prescribed time width obtained by a delay circuit is outputted. In such a case, the Q output (d) of the RS flip- flop circuit 12 is at L until the input signal (a) goes to L and reset to prevent the RS flip-flop circuit 11 from being set again.
申请公布号 JPS6359017(A) 申请公布日期 1988.03.14
申请号 JP19860200495 申请日期 1986.08.27
申请人 MITSUBISHI ELECTRIC CORP 发明人 AOKI KAZUO
分类号 H03K3/02;H03K5/00;H03K5/04;H03K5/1532 主分类号 H03K3/02
代理机构 代理人
主权项
地址