| 摘要 |
PURPOSE:To prevent arithmetic operation speed from decreasing in an execution unit, even when a general register is provided out-side the execution unit, by inputting a data supplied from the general register through a buffer register coupled directly to an arithmetic operation logic unit, to the arithmetic operation logic unit. CONSTITUTION:For instance, a general register group 8 consisting of plural register sets in which 16 pieces of registers form one set is provided outside the execution unit 6. A data in this general register group 8 can be supplied to a buffer register 9 coupled directly only to one input terminal of an arithmetic operation logic unit ALU, through a multiplexer MPX. Also, to the other input terminal of the arithmetic operation logic unit ALU, a read bus RB in the execution unit 6 is connected. That is to say, according to such a constitution, only the buffer register 9 is connected to one input terminal of the arithmetic operation logic unit ALU, and the read bus RB in the execution unit 6 is constituted of only one piece. In such a way, the speed for calculating an effective address, etc., is increased. |
