| 摘要 |
PURPOSE:To obtain a vector processor which can execute a vector operation even to data having undefined length by providing a completion deciding function concerning the contents of vector data. CONSTITUTION:A register 15, which is a register number next to a register 3, has the contents of the data as a completion condition. For example, the elements specified with the sum of the contents of a vector description table 5 and the register 2, from the vector data 10, is transmitted not only to a vector computing element 14 but also to a data comparator 16 so as to be compared with the contents of the register 15. When the result coincide, the vector operation is completed regardless of the result of a vector length comparator 6. When the results of the data comparator 15 do not coincide the vector length comparator 7 executes comparisons and if the contents of the register 2 is as same as or smaller than the contents of the register 3, the operation is executed in the vector computing element 14 to increase the contents of the register 2 by one. Namely, when either comparator 6 or 15 satisfies the completion condition the vector operation is completed. |
