| 摘要 |
<p>PURPOSE:To lower noise level without sacrificing the operating speed of reading of low-level output by distorting the logic threshold voltage for sense amplifiers that respectively receive read signals sequentially from the memory blocks in the order starting from the memory block close to a word line selection circuit sequentially. CONSTITUTION:The plural memory blocks M-ARY0-M-ARY7 are constituted to a common word line constituting a memory array M-ARY. The logic threshold voltage for the sense amplifiers SA0-SA7 that respectively receives a reading signal from the memory blocks M-ARY0-M-ARY7 in the order starting from the block M-ARY0 which is close to the word line selection circuit XDCR sequentially is distorted, in order to speed up the reading of storage information corresponding to the low level of output signals transmitted to an external terminal. Accordingly, since the read signals of storage information are outputted time-sequentially from said memory blocks in the order starting from the M-ARY0 close to the word line selection circuit XDCR sequentially the noise level can be lowered without sacrificing the operating speed of a reading of low-level output.</p> |
