| 摘要 |
PURPOSE:To contrive to stabilize the operation and to improve S/N by providing a PLL circuit synchronizing an over sampling clock and an internal sampling clock with a sampling clock extracted by a digital processing unit. CONSTITUTION:An analog signal subject to phase modulation or the like is converted by an A/D conversion circuit A/D of an A/D converter ADE of an A/D.D/A converter with the over sampling clock phiOS and fed to the digital processing unit DSP via a decimeter circuit DEC controlled by the internal sampling clock phis. The internal clock phis extracted by the unit DSP is subject to phase comparison with the clock phis2 outputted from the frequency divider circuit FD at the phase comparator circuit PFC of the PLL circuit and the variable frequency divider circuit VFD is controlled in response to the phase difference. Then the clock phiOS is outputted from the circuit VFD, the clock phis2 is outputted from the circuit FD receiving the clock OOS, the clocks phiOS and phis2 are synchronized with the clock phis while keeping a prescribed ratio, the operation is stabilized, malfunction is prevented and the S/N is improved. Moreover, the D/A conversion is applied similarly. |
