| 摘要 |
PURPOSE:To attain sufficiently practical error correction even in the burst data transmission by using an SOM to eliminate the phase ambiguity caused at demodulation and eliminating the phase ambiguity caused at serial conversion by a transmission/reception timing circuit. CONSTITUTION:A transmission timing circuit 1 receives a transmission clock signal 101, a transmission data signal 102, a transmission request signal 103 and a word frame signal 106, outputs a transmission data signal 104, a load signal 105 in synchronism with a signal 106 and sends a transmission request signal 107 to an SOM generating circuit 3. A parity code generating circuit 2 sends data signals 108, 109 of 1/2-frame each and a clock signal 110 to the circuit 3. A carrier signal 111 and the data signals 112, 113 eliminated with the phase ambiguity. On the other hand, the phase ambiguity is eliminated by a phase ambiguity elimination circuit 4 receiving an ACQ signal 114 from a demodulation section 7, data signals 115, 116 added by a parity code and a clock signal 117 and the timing circuit and the data are outputted via an error correction circuit 6. |
