| 摘要 |
PURPOSE:To improve the response characteristic by detecting a phase difference between a reference clock signal and an internal clock signal and controlling the frequency division ratio of a variable frequency division circuit if the result of detection exceeds a prescribed value. CONSTITUTION:A phase comparison circuit PFC outputs up/down up0/dw0 signals and gives them to AND gates AG1, AG2 respectively to which the 1st signal phiO of a phase difference decision circuit PDC in response to the phase difference between the reference clock phi1 and the frequency divider circuit FD. Then the output of an OR gate OG1 is counted by a counter circuit CTR and when the phase difference reaches a prescribed value or over, a control signal cg outputted from the circuit CTR goes to H aud the control signal generating circuit CSG outputs a control signal up or dw in response to the signal up0/dw0. The frequency division ratio of the variable frequency division circuit VFD is controlled by the signals up, dw, a very small phase difference is neglected, the response speed to the rapid phase fluctuation due to the fluctuation of power voltage is quickened, and the titled PLL circuit whose response characteristic is improved is attained. |
