| 摘要 |
PURPOSE:To obtain an output signal having a pulse width equal to that of an input signal without increasing the chip area by connecting a specific load externally to an output of an inverter by an odd number stage before an output inverter in a delay integrated circuit comprising plural inverters connected in series. CONSTITUTION:A pulse signal from an FM signal source 17 is delayed by even number of inverters each comprising CMOS transistors (7 and 12, 8 and 13, ...9 and 14, 10 and 15) and outputted to an FM demodulator 18 being a load of the like. A pulse width control circuit 19 for a specific load comprising a series resistor 20 and a capacitor 21 corresponding to the demodulator 18 being the load is connected to the output of the inverter by an odd number just before the final stage. The unsharpened output waveform of the just preceding inverter is adjusted by the specific load and the pulse width decided by the unsharpened waveform over the threshold value is adjusted the same width as that of the input pulse. Thus, it is not required to use the final stage inverter having a large drive capability, and the output signal becomes a signal having an equal pulse width to that of the input signal without increasing the chip area. |
