| 摘要 |
PURPOSE:To contrive to improve the processing capacity with a repetitive control arithmetic or an address arithmetic by providing a bypass to send data to a data bus from one of two outputs of a memory device with no intervention of an arithmetic device. CONSTITUTION:Two data are outputted to read output terminals 12 and 13 from a memory device 1 in a cycle t0 and then calculated by an arithmetic device in cycles t1 and t2, respectively. Then these calculated data are sent to the memory device 1 or a pipeline arithmetic device in a cycle t3 through a data bus 3. While in a data transfer mode the data are read out of the device 1 and sent to a read output terminal 13 in a cycle t1. Then these data are supplied to the device 1 o the pipeline arithmetic device in the cycle t2 from a bypass bus 4 via the bus 3. Then the processing capacity of a data processor for repetitive control arithmetic or address arithmetic greatly improved by performing the transfer of data simultaneously with arithmetic execution of the device 1. As a result, the addresses can be supplied to plural pipeline arithmetic devices just by a single arithmetic device. |
