| 摘要 |
PURPOSE:To reduce bus occupation time including dummy time up to start which is occupied by masters by providing the titled device with a delay circuit for delaying a bus use request signal outputted from a master to bus competition part by a prescribed time. CONSTITUTION:A master 11 out of plural masters 11-1n inputs dummy time up to a real start after the output of a bus request. A bus request signal outputted from the master 11 inputting the dummy time is inputted to a delay circuit 31, delayed by a fixed time and then applied to a priority deciding circuit 32. The circuit 32 decides priority based on the bus request signal applied with the delay of the fixed period and returns an allowable signal to the master. |
