Integrated memory circuit utilizing block selection.

摘要

Memory cells in an integrated memory circuit are arranged in blocks and selected by means of block selection gates. As is known, this method of activiation offers the advantage that the memory cells are accessed faster and that the power consumption is lower than in a memory which is not subdivided into blocks, because only a small group of memory cells is activated per selection operation. The invention provides a block selection circuit in which selection gates of two neighbouring rows of memory cells have one common transistor. As a result of the multiple use of contact areas and the use of a mirror-symmetrical architecture, the lay-out can make optimum use of the available substrate surface area.