| 摘要 |
A data processing apparatus employing a DMA system has a newly added circuit having a register in addition to the normal combination of a host processor, a memory and a DMA controller. The added circuit is provided between the host processor and the DMA controller. The host processor produces a setting signal by itself for setting a bus request signal into the register of the added circuit. The added circuit applies the bus request signal set in the register to the host processor without an access from the DMA controller. The host processor receives the bus request signal and sends a bus usage grant signal to the added circuit when the host processor does not need to use a bus or after a processing using the bus has been completed, and electrically cuts off itself from the bus. The DMA controller requests a bus usage to the added circuit when a DMA transmission is required. At this timing, since the bus is already in an idle state, a permission signal to permit a bus usage is immediately returned to the DMA controller. Therefore, a high-speed DMA transmission can be performed. Particularly, a quick response between the host processor and the DMA controller can be achieved by means of the added circuit.
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