| 摘要 |
An integrated circuit (10) that has logic (16) and a static random access memory (SRAM) array (18) has improved performance by treating the interlayer dielectric (ILD) (42, 40) differently for the SRAM array than for the logic. The N channel logic (20) and SRAM transistors (24, 26) have ILDs (40) with non-compressive stress, the P channel logic transistor (22) ILD (42) has compressive stress, and the P channel SRAM transistor (26) at least has less compressive stress than the P channel logic transistor (22), i.e., the P channel SRAM transistors (26) may be compressive but less so than the P channel logic transistors (22), may be relaxed, or may be tensile. It is beneficial for the integrated circuit (10) for the P channel SRAM transistors (26) to have a lower mobility than the P channel logic transistors (22). The P channel SRAM transistors (26) having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage. |
