发明名称 Logic circuit testable as an inverter pair and operable as a flip-flop
摘要 A logic circuit on a substrate is switchable between a test mode and an operational mode. First and second NOR gates are cross-coupled and may be switched between an operational mode and a test mode by the application of a control signal to first and second transfer gates coupled to the inputs of the NOR gates. The first NOR gate includes a p-type region and an n-type region formed in said substrate and traversed with first and second conductive layers insulated from the p and n-type regions. Thus, the first NOR gate includes two p-channel transistors and two n-channel transistors. The second NOR gate is also formed by a p-type region and an n-type region traversed with third and fourth conductive layers. Thus, the second NOR gate also includes two p-channel transistors and two n-channel transistors. The transfer gates are located on the substrate between the first and second NOR gates. Both transfer gates include an n-type region formed in the substrate with a conductive layer disposed over the n-type region. In the operational mode, the cross-coupled NOR gates may perform as a flip-flop. In the test mode, each NOR gate essentially becomes an inverter.
申请公布号 US4728823(A) 申请公布日期 1988.03.01
申请号 US19860888273 申请日期 1986.07.22
申请人 TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 发明人 KINOSHITA, TSUNEO
分类号 G01R31/28;G01R31/317;G06F11/22;H03K3/037;H03K3/356;H03K19/173;(IPC1-7):H03K3/356 主分类号 G01R31/28
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