| 摘要 |
A semiconductor memory device is comprised of memory cells arranged in a matrix fashion; defective row line detect circuits for producing logic "1" when a defective row line is selectd to which a detective cell is connected; defective column line detect circuits for producing a logical "1" signal when a defective column line is selected to which a defective cell is connected; an AND gate for detecting the selection of defective cell using a logic value of the output signals from defective row and column line detect circuits; and an exclusive OR gate for exclusively ORing the read out data signal and the output signal from the AND gate to correct the defective data.
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