发明名称 SUBTRACTION DEVICE
摘要 PURPOSE:To perform a basic action of subtraction in a simple circuit constitution and in a short time by using a data converting circuit which always fetches the binary number data on a data bus and delivers a complement of '2' and latches this complement to a register with a single clock. CONSTITUTION:The numeric value A is put on a data bus 1 and a clock CK1 is given to a register 2 to latch the value A to the latch 2. Then the numeric value B is put on the bus 1 and a clock CK2 is given to a register 4. The the numeric value -B obtained through conversion of the complement of '2' done by a data converting circuit 3 is latched by the register 4. The value A of the register 2 is added with the value -B of the register 4 by an addition circuit 5. Then A+(-B) is latched at a time point when the CK1 is given to the register 2. Thus one cycle is through in a period of time equivalent to three clocks.
申请公布号 JPS6346538(A) 申请公布日期 1988.02.27
申请号 JP19860190026 申请日期 1986.08.13
申请人 MATSUSHITA GRAPHIC COMMUN SYST INC 发明人 NOMA NOBUHIKO;TAKAGI GENZO
分类号 G06F7/50 主分类号 G06F7/50
代理机构 代理人
主权项
地址