| 摘要 |
PURPOSE:To reduce jitter by adding a circuit controlling a region where an output state of a frequency divider is unchanged to an input signal in the phase synchronizing state. CONSTITUTION:Suppose that an input signal frequency is close to 1/m frequency- division of a reference frequency. A phase comparator 3 detects a phase difference between an input signal fed to a terminal 1 and a signal from a frequency divider 6. A frequency division control circuit 4 sets a frequency division of 1/(m-1) or 1/(m+1) depending on the lead/lag of the phases, but the frequency division is fixed to 1/m only by a dead band control signal obtained via a blind sector control circuit 7 at regions before and after the leading change point of the output of the frequency divider and the output of the reference oscillator 5 is frequency-divided (6) by the output of the circuit 4. Its output is inputted to the comparator 3 and also outputted externally via a terminal 2 simultaneously. Further, part of the output of the frequency divider 6 is inputted to the blind sector control circuit 7. The pulse width of the signal of the circuit 7 is made close to the minimum clock width of the reference oscillator for the frequency divider. |
