| 摘要 |
<p>Increasing the storage capacity of high-performance (signal) processors while maintaining the original RAM cell necessitates modification of the entire lay-out of the circuit. The invention relates to the once-only design of peripheral circuitry which provides control of blocks of 4 Full CMOS RAM cells (easy to process) or 9 double-layer polysilicon cells (more difficult to process, but having smaller dimensions). It is defined in the RAM peripheral circuitry whether all 9 cells can be accessed (memory capacity from 2?**n to 2**¿(n+1) + 2**(n-2)) or 8 cells can be accessed (memory capacity from 2?*n to 2**¿(n+1)).</p> |
