发明名称 |
Testing embedded memory in an integrated circuit |
摘要 |
An integrated circuit includes a first bus and at least one array of embedded memories. Each array includes a second bus such as a bidirectional bus coupled to the embedded memories and to the first bus such that test vectors in the form of data words can be written from the first bus to selected embedded memories in the array. Also included is a built-in-self-test (BIST) circuit operable to compare data words on the first bus to data words read back from the selected embedded memories through the bidirectional bus.
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申请公布号 |
US7484144(B2) |
申请公布日期 |
2009.01.27 |
申请号 |
US20040929199 |
申请日期 |
2004.08.30 |
申请人 |
LATTICE SEMICONDUCTOR CORPORATION |
发明人 |
HAN WEI;MCLAURY LOREN |
分类号 |
G11C29/00;G06F11/00;G11C7/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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