发明名称 Memory addressing device
摘要 An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever the first word of the address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.
申请公布号 US4727481(A) 申请公布日期 1988.02.23
申请号 US19840670295 申请日期 1984.11.13
申请人 SOCIETE ANONYME DE TELECOMMUNICATIONS 发明人 AGUILLE, GERARD;JOLIVET, JEAN-CLAUDE R.
分类号 G11C5/06;G11C8/04;(IPC1-7):G06F7/00;G11C8/00 主分类号 G11C5/06
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