| 摘要 |
By examining parity for a bit combination representing the present phase state of a stepping motor, a selection can be made as to which phase state should be changed in order to produce rotation of the step motor in a predetermined direction. By including within the parity determination not only the present phase state of the stepping motor, but the logic level of a direction bit (DIR), appropriate phase sequence for either CW or CCW rotation can be selected. In a hardware embodiment of the invention, a conventional parity generator module is used with inputs representing the present motor phase states as well as a logic level for a DIR bit. The output of the parity generator then determines which phase state to change to produce the desired rotation. In a software embodiment, a digital computer dedicates a phase state byte with a bit from each motor phase state and an additional DIR bit. Parity can be determined using a conditional branch on parity instruction or merely summing the phase direction byte. In either event, the state of the motor phase is changed depending upon the result of the parity determination in order to produce the desired rotation.
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