| 摘要 |
PURPOSE:To obtain a false lock detecting circuit for setting easily a timing, by detecting the maximum amplitude of a difference frequency component from an output signal of an A/D converter identifying level by a timing whose phase is different by 180 deg. from that of the A/D converter identifying the level of I and Q channels. CONSTITUTION:The titled circuit is provided with A/D converters 1, 2 identifying the level of detecting output signals of I and Q channels, an A/D converter 3 for applying the detecting output signal of one of the I and Q channels to the A/D converters 1, 2, and a discriminating part 4, and in the discriminating part 4, the maximum amplitude of a difference frequency component is detected from an output signal of the A/D converter 3, and a false lock state or not is detected. A false lock detection timing is obtained by inverting a data identification timing by 180 deg., therefore, the timing can be set easily. Also, this circuit detects the maximum amplitude of a difference frequency component separated by 1/n on a cross point of an eye pattern, therefore, it is scarcely influenced by noise. |
