| 摘要 |
PURPOSE:To detect the abnormality of a bypass action in a pipeline system by checking the propriety of bypass data. CONSTITUTION:The updating data (a) of an instruction (a) proceeds successively each stage of a pipeline as an operand register 5, a writing register 6 and a buffer register 7 in response to clock cycles t2, t3 and t4. At the same time, the address (aw) of a general-purpose register as well which updates the instruction (a) proceeds to a register 11 and a register 12 together with the updating instruction address (aw) of the general-purpose register of the instruction (a) as well and is transferred to a register 81 and a register 82. In the cycle t3 an instruction (c) is set at a stage A together with an instruction (b) preceding the instruction (c) set at a stage B and the instruction (a) set at a stage C respectively. In such a case, it is checked that the signal BB of a register 88 is set at '1' and that the coincidence is secured between the operand data OD bypassed by the register 5 and the data WD(a') delivered from the register 6. In such a way, the propriety of the bypass data is monitored. |
