发明名称 ADDRESS BUS TEST CIRCUIT
摘要 PURPOSE:To quickly carry out tests for the abnormal working of a program and an address bus by setting an address where all address buses are set at '1' as well as a 0 address to an address bus and securing an exclusive OR between a signal line led from an input/output controller and said address bus. CONSTITUTION:A 0 address is set to an address bus line 12 and the comparison data is set at '0'. Then an exclusive OR is secured by an exclusive OR circuit 4 and therefore a stack '1' of the line 12 is known. Then an address FFFF is set to the line 12, the comparison data set at '1' respectively and an exclusive OR is secured by the circuit 4. Thus a stack '0' of the line 12 is obtained. In other words, if a signal adverse to an input signal is supplied to a part of the line 12, the exclusive logic element of that area has discordance of input. Then '1' is outputted from the logic element and an NOK signal is outputted to an output line 28.
申请公布号 JPS6339050(A) 申请公布日期 1988.02.19
申请号 JP19860182481 申请日期 1986.08.01
申请人 NEC CORP;NEC ENG LTD 发明人 SUZUKI MASAAKI;KOBAYASHI YOSHIAKI
分类号 G06F11/22;D01H1/18;G06F13/00 主分类号 G06F11/22
代理机构 代理人
主权项
地址