MASTERSLICE INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

摘要

In a masterslice integrated circuit, a plurality of input and output logic gates and a plurality of internal logic gates are arranged in the form of an array. A custom-made wiring pattern is arranged between the input and output logic gates and the internal logic gates. At least one of the logic gates comprises a plurality of PNP transistors (Q11 INFINITY Q15) and a plurality of output stage circuits (OSA, OSB). In addition, by the custom-made wiring pattern, one of the output stage circuits is connected to the emitter of at least one of the PNP transistors to form one of the logic gates.