| 摘要 |
PURPOSE:To obtain an integrated circuit device which facilitates a scan test including circuit blocks having asynchronous order circuits internally by providing scan registers and latch circuits connected to the scan registers among circuit blocks to be tested and at their connection parts. CONSTITUTION:The scan registers 8-16 provided among the circuit blocks 71-73 and at their connection parts and can be switched to a through-state. The latch circuits 17-25 are connected to the output terminals of the corresponding scan registers 8-16 and can be switched to a through-state similarly. In normal operation, the scan registers 8-16 and the latch circuits 17-25 connected to their output terminals are placed in a through-state to connect the input and output terminals of the corresponding circuit blocks 71-73. In test operation, the latch circuits 17-25 connected to the output terminals of the scan registers 8-16 are placed in a nonthrough-state to hold test data applied last time during a scan mode, thereby applying it to the corresponding circuit blocks 71-73 continuously. |
