| 摘要 |
PURPOSE:To transfer information beyond the depth of an FIFO register without increasing the processing time by providing the FIFO register between CPUs and requesting interruption from the receiving CPU when information is written in the FIFO register. CONSTITUTION:A CPU 100 on a transmission side transmits information to an information transfer signal line 106, and simultaneously gives instructions to write information in the FIFO register 102 through an instruction control signal line 104. Consequently one information is written in the register 102. The CPU 100 repeats said procedures until information to be transmitted disappears. On the other hand, an interruption control circuit 103 always supervises the state of the write instruction control signal line 104. The moment the CPU 100 writes the first information in the register 102, the circuit 103 transmits an interruption request to a CPU 101 on a reception side. Receiving the interruption request, the CPU 101 accepts transferred information through an information transfer signal line 107 until the contents in the register 102 become empty. |
