| 摘要 |
PURPOSE:To be able to miniaturize a cell and enhance its density thereby to obtain a highly integrated DRAM by previously patterning a polysilicon layer to form a storage capacitor, coating it with an insulating layer, then opening contact holes in the layer, and covering the holes with the polysilicon layer. CONSTITUTION:In the formation of a dynamic random access memory (DRAM) cell, the layers of a gate 3 and a storage capacitor are formed, the whole surface of a substrate is covered with an SiO2 layer 8 as an interlayer insulating layer, and in the layer on source, drain region 1A is formed a contact hole 9. The whole substrate is covered with a polysilicon layer 10 as a contact layer over the hole 9, and patterned larger than the hole 9. A field effect transistor (FET) is connected to a storage capacitor by means of a storage electrode 5 for electrically connecting to source, drain region 1B. The region 1A is brought ints contact through the layer 10 in the hole 9, and a bit line 12 made of aluminum is formed perpendicularly to a word line 3 through a phosphosilicate glass (PSG) layer 11 as a cover insulating layer on the substrate. |
