发明名称 DATA LOOP BACK SYSTEM
摘要 PURPOSE:To check easily the interface of an adapter by writing the data to a data buffer by the control of a DMA control circuit first, reading next the data from the data buffer and transferring them through the DMA control circuit to the memory in data loop back. CONSTITUTION:When a loop back test is executed, a DMA control circuit only is operated and the data of a memory 3 are stored into a data buffer 2. Next, a controller 6-0, a controller 6-1 and the DMA control circuit 4 are operated, and the data of the data buffer 5 are written through the controller 6-0, a signal line for the loop back, the controller 6-1, the DMA control circuit 4 and a bus to the memory 3. At first, the data may be written through the DMA control circuit 4, the controller 6-1, the signal line for the loop back and the controller 6-0 to the data buffer 5, and next, the data read from the data buffer 5 may be written through the DMA control circuit 4 to the memory 3.
申请公布号 JPS6336457(A) 申请公布日期 1988.02.17
申请号 JP19860180807 申请日期 1986.07.31
申请人 PFU LTD 发明人 KAZAMA SEIJI;OGAWA YOSHINARI
分类号 G06F13/00;G06F13/28 主分类号 G06F13/00
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