System clock distribution in a distributed computing environment

摘要

A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.

主权项

1. A method of distributing a system clock signal within a distributed computing system, the method comprising:
receiving a system clock signal of a first frequency from a clock source; providing the system clock signal to a first die of a plurality of interconnected die via a first input port of the first die; providing a copy of the system clock signal from the first die to a second die of the plurality of die via a first input port of the second die; sending a first signal comprising data from the first die to the second die over a send line of the first die, the send line of the first die configured to send data without receiving data; and receiving an acknowledgement signal at the first die, the acknowledgement signal received from the second die over the send line of the first die, wherein at least some of the plurality of interconnected die receive a master primary clock signal of the first frequency, wherein the master primary clock signal is based on the system clock signal, and wherein the master primary clock signal is distributed to the at least some of the plurality of interconnected die according to a system clock distribution network, and wherein at least one of the first die or the second die comprises a hardware processor.